Commit 3ae215b0 authored by Dave Gerlach's avatar Dave Gerlach Committed by Nishanth Menon

[AM437x][PRM] Add register definitions and register access support

Add all AM437X PRM register definitions and appropriate accessors
functions for use by 'dump prcm' command.
Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
parent fe031d11
......@@ -303,7 +303,9 @@ AM437XSOURCES=\
arch/arm/mach-omap/am437x/emif_am437x-defs.c\
arch/arm/mach-omap/am437x/emif_am437x.c\
arch/arm/mach-omap/am437x/prcm/cm_am437x-defs.c\
arch/arm/mach-omap/am437x/prcm/cm_am437x.c
arch/arm/mach-omap/am437x/prcm/cm_am437x.c\
arch/arm/mach-omap/am437x/prcm/prm_am437x-defs.c\
arch/arm/mach-omap/am437x/prcm/prm_am437x.c
AM437XOBJECTS= $(AM437XSOURCES:.c=.o)
......
/*
*
* @Component OMAPCONF
* @Filename prm_am437x-defs.c
* @Description AM437X PRM Register Definitions & Functions
* @Author Dave Gerlach <d-gerlach@ti.com>
* @Date 2016
* @Copyright Texas Instruments Incorporated
*
*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <prm_am437x-defs.h>
#include <stdio.h>
reg am437x_pm_cefuse_pwrstctrl = {
"PM_CEFUSE_PWRSTCTRL",
AM437X_PM_CEFUSE_PWRSTCTRL,
0xDEADBEEF,
0,
};
reg am437x_pm_cefuse_pwrstst = {
"PM_CEFUSE_PWRSTST",
AM437X_PM_CEFUSE_PWRSTST,
0xDEADBEEF,
0,
};
reg am437x_rm_cefuse_context = {
"RM_CEFUSE_CONTEXT",
AM437X_RM_CEFUSE_CONTEXT,
0xDEADBEEF,
0,
};
reg *am437x_prm_cefuse_mod[AM437X_PRM_CEFUSE_MOD_REGCOUNT + 1] = {
&am437x_pm_cefuse_pwrstctrl,
&am437x_pm_cefuse_pwrstst,
&am437x_rm_cefuse_context,
NULL,
};
reg am437x_prm_rstctrl = {
"PRM_RSTCTRL",
AM437X_PRM_RSTCTRL,
0xDEADBEEF,
0,
};
reg am437x_prm_rstst = {
"PRM_RSTST",
AM437X_PRM_RSTST,
0xDEADBEEF,
0,
};
reg am437x_prm_rsttime = {
"PRM_RSTTIME",
AM437X_PRM_RSTTIME,
0xDEADBEEF,
0,
};
reg am437x_prm_sram_count = {
"PRM_SRAM_COUNT",
AM437X_PRM_SRAM_COUNT,
0xDEADBEEF,
0,
};
reg am437x_prm_ldo_sram_core_setup = {
"PRM_LDO_SRAM_CORE_SETUP",
AM437X_PRM_LDO_SRAM_CORE_SETUP,
0xDEADBEEF,
0,
};
reg am437x_prm_ldo_sram_core_ctrl = {
"PRM_LDO_SRAM_CORE_CTRL",
AM437X_PRM_LDO_SRAM_CORE_CTRL,
0xDEADBEEF,
0,
};
reg am437x_prm_ldo_sram_mpu_setup = {
"PRM_LDO_SRAM_MPU_SETUP",
AM437X_PRM_LDO_SRAM_MPU_SETUP,
0xDEADBEEF,
0,
};
reg am437x_prm_ldo_sram_mpu_ctrl = {
"PRM_LDO_SRAM_MPU_CTRL",
AM437X_PRM_LDO_SRAM_MPU_CTRL,
0xDEADBEEF,
0,
};
reg am437x_prm_io_count = {
"PRM_IO_COUNT",
AM437X_PRM_IO_COUNT,
0xDEADBEEF,
0,
};
reg am437x_prm_io_pmctrl = {
"PRM_IO_PMCTRL",
AM437X_PRM_IO_PMCTRL,
0xDEADBEEF,
0,
};
reg am437x_prm_vc_val_bypass = {
"PRM_VC_VAL_BYPASS",
AM437X_PRM_VC_VAL_BYPASS,
0xDEADBEEF,
0,
};
reg am437x_prm_emif_ctrl = {
"PRM_EMIF_CTRL",
AM437X_PRM_EMIF_CTRL,
0xDEADBEEF,
0,
};
reg *am437x_prm_device_mod[AM437X_PRM_DEVICE_MOD_REGCOUNT + 1] = {
&am437x_prm_rstctrl,
&am437x_prm_rstst,
&am437x_prm_rsttime,
&am437x_prm_sram_count,
&am437x_prm_ldo_sram_core_setup,
&am437x_prm_ldo_sram_core_ctrl,
&am437x_prm_ldo_sram_mpu_setup,
&am437x_prm_ldo_sram_mpu_ctrl,
&am437x_prm_io_count,
&am437x_prm_io_pmctrl,
&am437x_prm_vc_val_bypass,
&am437x_prm_emif_ctrl,
NULL,
};
reg am437x_prm_pm_gfx_pwrstctrl = {
"PRM_PM_GFX_PWRSTCTRL",
AM437X_PRM_PM_GFX_PWRSTCTRL,
0xDEADBEEF,
0,
};
reg am437x_prm_pm_gfx_pwrstst = {
"PRM_PM_GFX_PWRSTST",
AM437X_PRM_PM_GFX_PWRSTST,
0xDEADBEEF,
0,
};
reg am437x_prm_rm_gfx_rstctrl = {
"PRM_RM_GFX_RSTCTRL",
AM437X_PRM_RM_GFX_RSTCTRL,
0xDEADBEEF,
0,
};
reg am437x_prm_rm_gfx_rstst = {
"PRM_RM_GFX_RSTST",
AM437X_PRM_RM_GFX_RSTST,
0xDEADBEEF,
0,
};
reg am437x_prm_rm_gfx_context = {
"PRM_RM_GFX_CONTEXT",
AM437X_PRM_RM_GFX_CONTEXT,
0xDEADBEEF,
0,
};
reg *am437x_prm_gfx_mod[AM437X_PRM_GFX_MOD_REGCOUNT + 1] = {
&am437x_prm_pm_gfx_pwrstctrl,
&am437x_prm_pm_gfx_pwrstst,
&am437x_prm_rm_gfx_rstctrl,
&am437x_prm_rm_gfx_rstst,
&am437x_prm_rm_gfx_context,
NULL,
};
reg am437x_pm_mpu_pwrstctrl = {
"PM_MPU_PWRSTCTRL",
AM437X_PM_MPU_PWRSTCTRL,
0xDEADBEEF,
0,
};
reg am437x_pm_mpu_pwrstst = {
"PM_MPU_PWRSTST",
AM437X_PM_MPU_PWRSTST,
0xDEADBEEF,
0,
};
reg am437x_rm_mpu_rstst = {
"RM_MPU_RSTST",
AM437X_RM_MPU_RSTST,
0xDEADBEEF,
0,
};
reg am437x_rm_mpu_context = {
"RM_MPU_CONTEXT",
AM437X_RM_MPU_CONTEXT,
0xDEADBEEF,
0,
};
reg *am437x_prm_mpu_mod[AM437X_PRM_MPU_MOD_REGCOUNT + 1] = {
&am437x_pm_mpu_pwrstctrl,
&am437x_pm_mpu_pwrstst,
&am437x_rm_mpu_rstst,
&am437x_rm_mpu_context,
NULL,
};
reg am437x_pm_per_pwrstctrl = {
"PM_PER_PWRSTCTRL",
AM437X_PM_PER_PWRSTCTRL,
0xDEADBEEF,
0,
};
reg am437x_pm_per_pwrstst = {
"PM_PER_PWRSTST",
AM437X_PM_PER_PWRSTST,
0xDEADBEEF,
0,
};
reg am437x_rm_per_rstctrl = {
"RM_PER_RSTCTRL",
AM437X_RM_PER_RSTCTRL,
0xDEADBEEF,
0,
};
reg am437x_rm_per_rstst = {
"RM_PER_RSTST",
AM437X_RM_PER_RSTST,
0xDEADBEEF,
0,
};
reg am437x_rm_per_l3_context = {
"RM_PER_L3_CONTEXT",
AM437X_RM_PER_L3_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_l3_instr_context = {
"RM_PER_L3_INSTR_CONTEXT",
AM437X_RM_PER_L3_INSTR_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_ocmcram_context = {
"RM_PER_OCMCRAM_CONTEXT",
AM437X_RM_PER_OCMCRAM_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_vpfe0_context = {
"RM_PER_VPFE0_CONTEXT",
AM437X_RM_PER_VPFE0_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_vpfe1_context = {
"RM_PER_VPFE1_CONTEXT",
AM437X_RM_PER_VPFE1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_tpcc_context = {
"RM_PER_TPCC_CONTEXT",
AM437X_RM_PER_TPCC_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_tptc0_context = {
"RM_PER_TPTC0_CONTEXT",
AM437X_RM_PER_TPTC0_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_tptc1_context = {
"RM_PER_TPTC1_CONTEXT",
AM437X_RM_PER_TPTC1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_tptc2_context = {
"RM_PER_TPTC2_CONTEXT",
AM437X_RM_PER_TPTC2_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_dll_aging_context = {
"RM_PER_DLL_AGING_CONTEXT",
AM437X_RM_PER_DLL_AGING_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_l4hs_context = {
"RM_PER_L4HS_CONTEXT",
AM437X_RM_PER_L4HS_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_gpmc_context = {
"RM_PER_GPMC_CONTEXT",
AM437X_RM_PER_GPMC_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_adc1_context = {
"RM_PER_ADC1_CONTEXT",
AM437X_RM_PER_ADC1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_mcasp0_context = {
"RM_PER_MCASP0_CONTEXT",
AM437X_RM_PER_MCASP0_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_mcasp1_context = {
"RM_PER_MCASP1_CONTEXT",
AM437X_RM_PER_MCASP1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_mmc2_context = {
"RM_PER_MMC2_CONTEXT",
AM437X_RM_PER_MMC2_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_qspi_context = {
"RM_PER_QSPI_CONTEXT",
AM437X_RM_PER_QSPI_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_usb_otg_ss0_context = {
"RM_PER_USB_OTG_SS0_CONTEXT",
AM437X_RM_PER_USB_OTG_SS0_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_usb_otg_ss1_context = {
"RM_PER_USB_OTG_SS1_CONTEXT",
AM437X_RM_PER_USB_OTG_SS1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_pru_icss_context = {
"RM_PER_PRU_ICSS_CONTEXT",
AM437X_RM_PER_PRU_ICSS_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_l4ls_context = {
"RM_PER_L4LS_CONTEXT",
AM437X_RM_PER_L4LS_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_dcan0_context = {
"RM_PER_DCAN0_CONTEXT",
AM437X_RM_PER_DCAN0_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_dcan1_context = {
"RM_PER_DCAN1_CONTEXT",
AM437X_RM_PER_DCAN1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_pwmss0_context = {
"RM_PER_PWMSS0_CONTEXT",
AM437X_RM_PER_PWMSS0_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_pwmss1_context = {
"RM_PER_PWMSS1_CONTEXT",
AM437X_RM_PER_PWMSS1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_pwmss2_context = {
"RM_PER_PWMSS2_CONTEXT",
AM437X_RM_PER_PWMSS2_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_pwmss3_context = {
"RM_PER_PWMSS3_CONTEXT",
AM437X_RM_PER_PWMSS3_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_pwmss4_context = {
"RM_PER_PWMSS4_CONTEXT",
AM437X_RM_PER_PWMSS4_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_pwmss5_context = {
"RM_PER_PWMSS5_CONTEXT",
AM437X_RM_PER_PWMSS5_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_elm_context = {
"RM_PER_ELM_CONTEXT",
AM437X_RM_PER_ELM_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_gpio1_context = {
"RM_PER_GPIO1_CONTEXT",
AM437X_RM_PER_GPIO1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_gpio2_context = {
"RM_PER_GPIO2_CONTEXT",
AM437X_RM_PER_GPIO2_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_gpio3_context = {
"RM_PER_GPIO3_CONTEXT",
AM437X_RM_PER_GPIO3_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_gpio4_context = {
"RM_PER_GPIO4_CONTEXT",
AM437X_RM_PER_GPIO4_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_gpio5_context = {
"RM_PER_GPIO5_CONTEXT",
AM437X_RM_PER_GPIO5_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_hdq1w_context = {
"RM_PER_HDQ1W_CONTEXT",
AM437X_RM_PER_HDQ1W_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_i2c1_context = {
"RM_PER_I2C1_CONTEXT",
AM437X_RM_PER_I2C1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_i2c2_context = {
"RM_PER_I2C2_CONTEXT",
AM437X_RM_PER_I2C2_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_mailbox0_context = {
"RM_PER_MAILBOX0_CONTEXT",
AM437X_RM_PER_MAILBOX0_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_mmc0_context = {
"RM_PER_MMC0_CONTEXT",
AM437X_RM_PER_MMC0_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_mmc1_context = {
"RM_PER_MMC1_CONTEXT",
AM437X_RM_PER_MMC1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_spi0_context = {
"RM_PER_SPI0_CONTEXT",
AM437X_RM_PER_SPI0_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_spi1_context = {
"RM_PER_SPI1_CONTEXT",
AM437X_RM_PER_SPI1_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_spi2_context = {
"RM_PER_SPI2_CONTEXT",
AM437X_RM_PER_SPI2_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_spi3_context = {
"RM_PER_SPI3_CONTEXT",
AM437X_RM_PER_SPI3_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_spi4_context = {
"RM_PER_SPI4_CONTEXT",
AM437X_RM_PER_SPI4_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_spinlock_context = {
"RM_PER_SPINLOCK_CONTEXT",
AM437X_RM_PER_SPINLOCK_CONTEXT,
0xDEADBEEF,
0,
};
reg am437x_rm_per_timer2_context = {
"RM_PER_TIMER2_CONTEXT",
AM437X_RM_PER_TIMER2_CONTEXT,
0xDEADBEEF,
0,
};