1. 21 Jul, 2018 6 commits
  2. 01 Jul, 2018 3 commits
  3. 27 Jun, 2018 1 commit
  4. 29 May, 2018 2 commits
    • Tony Lindgren's avatar
      LC15: Increase T_RFC to fix 4GB kernel memory errors · 2b143578
      Tony Lindgren authored
      With u-boot related memory errors out of the way fixed with patch
      "LC15: Fix flakey ddr3 detection with ref_ctrl and ref_ctrl_final",
      we can now narrow down the kernel related errors easily.
      
      Playing with timing changes I narrowed down the kernel hangs to register
      sdram_tim3 where we need to increase the time for T_RFC. This is for
      "Minimum number of DDR clock cycles from Refresh or Load Mode to Refresh
      or Activate, minus one" according to omap5432 TRM.
      
      Maxing out the value for bits 12:4 made the new 4GB pyra's C02 and C03
      boot reliably. And then looking at the timings again, the T_RFC value
      should be 187 - 1 (0xBA) and not 139 - 1 (0x8A). Note the Upper case
      B vs 8 :)
      
      Value 187 - 1 (0xBA) matches Samsung K4B8G1646D-MYK0 datasheet
      "[ Table 34 ] Timing used for IDD and IDDQ Measured - Loop Patterns"
      for DDR3-1066 8Gb memory. We are currently using 4Gb value 139 - 1
      (0x8A).
      
      It is possible that this was caused by B vs 8 typo initially and then
      was not noticed because of the u-boot memory errors and getting confused
      with the memory datasheet for 4Gb vs 4GB while we have four 8Gb memory
      chips.
      
      However I also noticed that value 187 - 1 (0xBA) still won't work
      reliably with new board C05. And new C21 and my older revision board
      C50 still did not work at all. However, using value of 191 - 1 (0xBE)
      makes all of them boot reliably for me. So let's use value 191 - 1
      (0xBE) for now, and adjust it if needed based on testing with more
      pyras.
      
      Note that we still can have pyra hang running two instances of
      memtester 1500M for about 10 minutes on bare CPU boards with no heat
      sink connected. The boards now boot reliably after that though,
      so presumably the pyra heat sink will solve this issue.
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      2b143578
    • Tony Lindgren's avatar
      LC15: Fix flakey ddr3 detection with ref_ctrl and ref_ctrl_final · babb512f
      Tony Lindgren authored
      Since commit 802bb57a ("ARM: DRA7: EMIF: Update SDRAM_REF_CTRL
      register value") we now do this in two phases.
      
      We are not currently configuring ref_ctrl and this seems to cause
      bogus memory errors early in u-boot that often happen if the board
      has been powered off for a while:
      
      SDRAM: identified size not same as expected size identified: 0
      expected: 40000000
      ...
      WARNING: DDR RAM is not working! (12000000)
      ...
      ### ERROR ### Please RESET the board ###
      
      Note that this does not solve the kernel related memory issues,
      but gets us to the point where u-boot starts reliably.
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      babb512f
  5. 28 May, 2018 2 commits
  6. 22 Feb, 2018 1 commit
  7. 21 Feb, 2018 2 commits
  8. 18 Dec, 2017 2 commits
  9. 30 Nov, 2017 1 commit
  10. 31 Jul, 2017 1 commit
  11. 13 Jul, 2017 1 commit
  12. 10 Jul, 2017 3 commits
  13. 26 Apr, 2017 1 commit
  14. 24 Apr, 2017 4 commits
  15. 24 Mar, 2017 1 commit
  16. 17 Mar, 2017 1 commit
  17. 28 Feb, 2017 6 commits
  18. 26 Feb, 2017 2 commits