Commit babb512f authored by Tony Lindgren's avatar Tony Lindgren Committed by H. Nikolaus Schaller

LC15: Fix flakey ddr3 detection with ref_ctrl and ref_ctrl_final

Since commit 802bb57a ("ARM: DRA7: EMIF: Update SDRAM_REF_CTRL
register value") we now do this in two phases.

We are not currently configuring ref_ctrl and this seems to cause
bogus memory errors early in u-boot that often happen if the board
has been powered off for a while:

SDRAM: identified size not same as expected size identified: 0
expected: 40000000
...
WARNING: DDR RAM is not working! (12000000)
...
### ERROR ### Please RESET the board ###

Note that this does not solve the kernel related memory issues,
but gets us to the point where u-boot starts reliably.
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 574cfd75
...@@ -40,7 +40,8 @@ const struct emif_regs emif_regs_ddr3_532_mhz_2cs_es2 = { ...@@ -40,7 +40,8 @@ const struct emif_regs emif_regs_ddr3_532_mhz_2cs_es2 = {
.sdram_config_init = 0x61851B3A, .sdram_config_init = 0x61851B3A,
.sdram_config = 0x61851B3A, .sdram_config = 0x61851B3A,
.sdram_config2 = 0x0, .sdram_config2 = 0x0,
.ref_ctrl = 0x00001035, .ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF36B3, .sdram_tim1 = 0xCCCF36B3,
.sdram_tim2 = 0x308F7FDA, .sdram_tim2 = 0x308F7FDA,
.sdram_tim3 = 0x027F88A8, .sdram_tim3 = 0x027F88A8,
......
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