• Lokesh Vutla's avatar
    ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value · 802bb57a
    Lokesh Vutla authored
    The value in SDRAM_REF_CTRL controls the delay time between
    the initial rising edge of DDR_RESETn to rising edge of DDR_CKE
    (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL
    should be written with a value corresponding to 500us delay before
    starting DDR initialization sequence, and configure proper
    value at the end of sequence.
    Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
    802bb57a
emif.h 37.6 KB