Commit 8d28294f authored by David Shah's avatar David Shah
Browse files

emif: Enable DLL only for calibration



On about 10% of Pyra units, the DLL must be enabled for calibration to
pass successfully.

But the DLL must be disabled for the kernel, or we hit another
self-refresh related issue...
Signed-off-by: default avatarDavid Shah <dave@ds0.me>
parent 8e417ba8
......@@ -375,7 +375,7 @@ static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
&emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->sdram_config_init & ~EMIF_REG_DDR_DISABLE_DLL_MASK, &emif->emif_sdram_config);
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
* and RL =7. As the default values of the Mode Registers are not
......@@ -394,13 +394,17 @@ static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->sdram_config_init & ~EMIF_REG_DDR_DISABLE_DLL_MASK, &emif->emif_sdram_config);
do_ext_phy_settings(base, regs);
__udelay(1000);
writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
omap5_ddr3_leveling(base, regs);
__udelay(1000);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
}
static void ddr3_init(u32 base, const struct emif_regs *regs)
......
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